Risc And Cisc
The primary goal of CISC architecture is to complete a task in as few instructions as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations, whereas RISC processors breaks down the instructions into simple steps (CISC vs. RISC, 2007). The concept RISC and CISC can be better explained using the following analogy.
John, your 10 year old son has been very naughty and as a result you punish him by giving him a lot of household chores. A typical CISC instruction set would say: clean your room, mop the kitchen floor, trim the garden, mow the lawn, clean the garage, wash the car, do the laundry, take out the trash… you get the picture? A typical RISC instruction would break down all those chores into simple steps, it could highlight each chore (for example: Clean your room, then mop the kitchen floor…) or it could even go as far as listing the steps to be taken to perform each chore (i.e. to clean the room he would have to: keep his toys back in the toy box, make the bed, neatly fold his clothes into his wardrobe…and so on). As we can see, RISC simply breaks down the tasks into simpler steps.
The RISC architecture use simple instructions that can be executed within one clock cycle- the time taken for the computer clock to oscillate once, it is measures in hertz(Hz) (Brookshear, 2008: 115). RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers in the CPU. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining- which allows steps in the machine cycle to overlap (i.e. while one instruction is executed, the next instruction can be fetched) (Brookshear, 2008: 129) is possible. One advantage of the RISC architecture is that fewer instructions are needed to implement a particular computing task, which leads to lower memory use for program storage and fewer...
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